Currently, bit lines of a cell of a DRAM (Dynamic Random Access Memory) are prevalently formed of tungsten. It is noted that lowering the resistance of the bit lines bears significantly on device miniaturization. To lower the resistance of the bit lines, it is necessary to make a conductor as large in diameter or in thickness as possible. One of means for increasing the diameter of the conductor is a SAC (Self-Aligned Contact) structure which allows increasing the diameter of the conductor without the necessity of taking account of alignment tolerance of the conductor with respect to a contact therefor.
FIGS. 7A-7C and FIGS. 8A-8C show a method used for manufacturing bit lines for a DRAM by SAC of a type such as disclosed in Patent Document 1.
Initially, a cell contact metal part 4 is formed and a bit contact metal part, not shown, is formed thereon. A contact metal part interlayer insulating film 8 is then deposited over the cell contact metal part 4 (see FIG. 7A). The contact metal part interlayer insulating film 8 is referred to below as a ‘contact interlayer film 8’. A laminate (dual-layer) film 11, formed by a polysilicon film and a layer of high-melting low-resistance metal part, is then deposited on the contact interlayer film 8. The laminate film is to form a bit line. A hard mask film 7, which is a silicon nitride film, is then deposited thereon (see FIG. 7B). The hard mask film 7 and the laminate film (11 of FIG. 7B) are then patterned to form bit lines 2 (see FIG. 7C).
A silicon nitride film is then formed on the entire surface of the contact interlayer film 8 inclusive of the bit line 2. This silicon nitride film is then etched back to form a sidewall 3 on a lateral surface of the bit line 2 (see FIG. 8A). A capacitive contact metal part interlayer insulating film 6, used to form a capacitive contact metal part (1 of FIG. 8C), is then deposited. The capacitive contact metal part interlayer insulating film 6 is referred to below as a ‘capacitive contact interlayer film 6’. After planarizing the surface by annealing, etchback or CMP (see FIG. 8B), the capacitive contact interlayer film 6 and the contact interlayer film 8 are removed by patterning to expose the cell contact metal part 4 to form a self-aligned contact hole. This self-aligned contact hole is then filled with the capacitive contact metal part 1 (see FIG. 8C).
In Patent Document 2, there is disclosed a method for manufacturing a semiconductor integrated circuit. Specifically, in a DRAM having an information storage capacitance device on top of a bit line, a trench for a conductor is formed in an insulating film deposited on a gate electrode operating as a word line of the DRAM. The conductor is formed in this insulating film. A sidewall spacer is constructed on a lateral surface of the trench for the conductor. A bit line, formed as a tungsten film, for example, is deposited in the trench for the conductor, the width of which has been narrowed by the sidewall spacer. The bit line is connected via a connection plug to the semiconductor substrate, and the bit line is connected to the connection plug at the bottom of the trench for the conductor.    [Patent Document 1]    JP Patent Kokai Publication No. JP2002-231906A    [Patent Document 2]    JP Patent Kokai Publication No. JP2005-252289A